ECE Department

Organizing a Six Days Technical Skill Enhancement Workshop


SRAM Design (Specs Finalization to Tapeout)

at BVCOE, New Delhi 



Objectives and Importance of the Workshop:

The objective of the program is to train the faculties/researchers/students into the technicalities of SRAM design.  Further aim of the training is to provide the industry practiced skilled procedures to the participants enabling them to initiate good quality works based on SRAM.

Importance of SRAM:

SRAM is used in the cache memory of a computing system or as part of the RAM digital to analog converter on a video card. Static RAM is also used for high-speed registers, caches and small memory banks like a frame buffer on a display adapter. Several scientific and industrial subsystems, modern appliances, automotive electronics, electronic toys, mobile phones, synthesizers and digital cameras also use SRAM. It is also highly recommended for use in PCs, peripheral equipment, printers, LCD screens, hard disk buffers, router buffers and buffers in CDROM / CDRW drives.

An SRAM is designed to fill two needs: to provide a direct interface with the CPU at speeds not attainable by DRAMs and to replace DRAMs in systems that require very low power consumption. In the first role, the SRAM serves as cache memory, interfacing between DRAMs and the CPU.

Another driving force for SRAM technology is low power applications. In this case, SRAMs are used in most portable equipment because the DRAM refresh current is several orders of magnitude more than the low-power SRAM standby current.

There are many reasons to use an SRAM or a DRAM in a system design. Design tradeoffs include density, speed, volatility, cost, and features

Some Characteristic of the Static RAM are, It has long life, There is no need to refresh, Faster, Used as cache memory, Large size, Expensive, High power consumption

Topics Targeted

  1. SRAM architectures ( including all building blocks, different options/ variations in SRAM memory architectures)
  2. Size issues in recharge, discharge, row decoder, column decoder, sense amplifier, SRAM cell, and other building blocks. Methodologies to address these size issues. Best followed practice for these.
  3. Partitioning of high capacity SRAM into banks and Design-Engineering involved with trade-offs/ limitations/advantages etc.
  4. Theory and methodologies of all SRAM- Analysis  ( static and dynamic-  RM, WR, read and write timing/delays, WNM, N curve, NNM, DRV, Iread, Iread/off, Power calculations, hold state analysis, MC oriented variation  ...etc{ required for a successful design of SRAM) 
  5. SRAM memory controller and design aspects
  6. Interleaved SRAM
  7. Read/Write assist circuits
  8. Low Power strategies for SRAM
  10. Layout strategies for SRAM
  11. NBTI and RTN issues and modeling
  12. Research aspects/scopes  and challenges 

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